The present invention relates to a noise eliminating CMOS circuit to be employed in a semiconductor integrated circuit.
FIG. 10(B) shows the standard symbol for an inverter circuit, which may be constituted by a CMOS integrated circuit. As shown in FIG. 10(A), the inverter circuit may be configured as follows. The gate of a PMOS transistor P1, the source of which is connected to a power supply voltage Vcc, and the gate of a NMOS transistor N1, the source of which is grounded, are each connected to a common input terminal. At the same time, the drain of the PMOS transistor P1 and that of the NMOS transistor N1 are each connected to a common output terminal. Depending on the voltage of an input signal inputted to the input terminal, the inverter circuit outputs an output signal at a "High" level or a "Low" level from the output terminal. Namely, when the input signal is higher than a logical threshold voltage VLT, the PMOS transistor P1 is in an OFF state and the NMOS transistor N1 is in an ON state, and thus the inverter circuit outputs a signal at a "Low" level from the output terminal. When the input signal is lower than the logical threshold voltage VLT, the PMOS transistor P1 is in an ON state and the NMOS transistor N1 is in an OFF state, and thus the inverter circuit outputs a signal at a "High" level from the output terminal.
When a noise is induced into the input signal, if a peak voltage of the noise does not attain the logical threshold voltage VLT, as represented by noise 1 or noise 3 in FIG. 11, neither the PMOS transistor P1, nor the NMOS transistor N1 performs a switching operation, and so the noise is not transmitted to the output signal. If, however, the peak voltage of the noise reaches or exceeds the logical threshold voltage VLT, as represented by noise 2 or 4 in FIG. 11, both the PMOS transistor P1 and the NMOS transistor N1 perform a switching operation, thus transmitting the noise to the output signal as represented by noise 5 or noise 6. The configuration of the inverter shown in FIG. 10(A) is described in "Hitachi LCD Controller/Driver LSI Data Book, 8th Edition".
Also, FIG. 12 shows the standard symbol for a Schmitt trigger circuit, i.e. one of the circuits which aim at eliminating noise and which have been employed in a semiconductor integrated circuit for this purpose. The circuit in FIG. 12 has a hysteresis characteristic in the input voltage, i.e. two logical threshold voltages, as will be described with reference to FIG. 13. When an input signal is higher than a first logical threshold voltage VIH, the circuit outputs a signal at a "Low" level from the output terminal, and when the input signal is lower than a second logical threshold voltage VIL, the circuit outputs a signal at a "High" level from the output terminal. In the operation of this circuit, there exists the relation that "the second logical threshold voltage VIL"&lt;"the first logical threshold voltage VIM". When a noise is induced into the input signal, if a peak voltage of the noise does not attain the first logical threshold voltage VIH or the second logical threshold voltage VIL, as represented by noise 1 or noise 3 in FIG. 13, the noise is not transmitted to the output signal. If, however, the peak voltage of the noise attains the first logical threshold voltage VIH or the second logical threshold voltage VIL, as represented by noise 2 or 4 in FIG. 13, the noise is transmitted to the output as a noise 5 or noise 6. The Schmitt trigger circuit, compared with the circuit shown in FIG. 10(A), has a higher ability to eliminate noise, because the first logical threshold voltage VIH is nearer to Vcc than the logical threshold voltage VLT and the second logical threshold voltage VIL is nearer to GND than the logical threshold voltage VLT. Characteristics of the Schmitt trigger circuit are described in detail in, for example, "HD74LS14" in "Hitachi TTL Data Book HD74/74S/74LS/74AS/75/26/29 Series, 4th Edition", or "HD74HC14" in "Hitachi High Speed CMOS Logic Data Book".
In the above-described inverter, if the peak voltage of a noise component does not exceed the logical threshold voltage VLT, the noise is not transmitted to the output signal, but if the peak voltage of the noise component exceeds the logical threshold voltage VLT, the noise is transmitted to the output signal.
In the above-described Schmitt trigger circuit, if the peak voltage of noise component does not exceed the first logical threshold voltage VIH or the second logical threshold voltage VIL, depending on the level of the input signal, the noise is not transmitted to the output. If, however, the peak voltage of the noise exceeds the first logical threshold voltage VIH or the second logical threshold voltage VIL, the noise is transmitted to the output. This gives rise to the possibility of a malfunction or a false operation of the semiconductor integrated circuit.
If the first logical threshold voltage VIH in the Schmitt trigger circuit is set at a level nearer to the Vcc electric potential and, in addition the second logical threshold voltage VIL is set at a level nearer to the GND electric potential, the sensitivity for noise decreases. However, when the semiconductor integrated circuit equipped with such an input circuit is connected with an output of some other semiconductor integrated circuit, there arises a necessity for generating an output which is extremely close to the electric potential of Vcc or GND. A semiconductor integrated circuit with such an output characteristic is not so realistic or practical.